The present invention relates to packaged microelectronic elements, packages therefor, and methods of packaging microelectronic elements.
Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. Most commonly, such packages include a dielectric element, commonly referred to as a “chip carrier” with package contacts formed as plated or etched metallic structures on the dielectric element. These package contacts typically are connected to the contacts, e.g. bond pads, of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces. In a surface mounting operation, the package is placed onto a circuit board so that each contact on the package is aligned with a corresponding terminal on a circuit panel, e.g., a circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or “reflow” the solder or otherwise activate the bonding material.
Considerable effort has been devoted in the art to making such packages smaller, so that the packaged chip occupies a smaller area on the circuit board. For example, packages referred to as chip-scale packages occupy an area of the circuit board equal to the area of the chip itself, or only slightly larger than the area of the chip itself. However, even with chip-scale packages, the aggregate area occupied by several packaged chips is greater than or equal to the aggregate area of the individual chips.
It has been proposed to provide “stacked” packages, in which a plurality of individual packaged chips or units are mounted one above the other in a common package assembly. This common package assembly can be mounted on an area of the circuit panel which may be equal to or just slightly larger than the area typically required to mount a single package or unit containing a single chip. The stacked package approach conserves space on the circuit panel. Chips or other elements which are functionally related to one another can be provided in a common stacked package assembly. The assembly may incorporate interconnections between these elements.
One form of stacked package assembly which has been proposed heretofore is sometimes referred to as a “ball stack.” A ball stack assembly includes two or more individual units. Each unit incorporates a unit substrate similar to the package substrate of an individual unit, and one or more microelectronic elements mounted to the unit substrate and connected to the terminals on the unit substrate. The individual units are stacked one above the other, with the terminals on each individual unit substrate being connected to terminals on another unit substrate by electrically conductive elements such as solder balls or pins. The terminals of the bottom unit substrate may constitute the terminals of the entire assembly or, alternatively, an additional substrate may be mounted at the bottom of the assembly which may have terminals connected to the terminals of the various unit substrates. Ball stack packages are depicted, for example, in certain preferred embodiments of U.S. Published Patent Applications 2003/0107118 and 2004/0031972, the disclosures of which are hereby incorporated by reference herein.
The substrate used to mount the chips also affects the size and thickness of the packaged chip. The substrate materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, neat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates.
Tapes have also been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip scale packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.
Despite all of the innovations discussed above, there remains room for improvement.